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features ? stereo audio dac ? 2.7v to 3.3v analog supply operation ? 2.4v to 3.3v digital supply operation ? 20-bit stereo audio dac ? 93 db snr playback stereo channels ? 32 ohm/20 mw stereo headset drivers wi th master volume and mute controls ? stereo line level input with volume control/mute and playback through the headset drivers ? differential monaural auxiliary input, with volume control/mute and playback through the headset drivers ? accepts mixed signals from all signal paths (l ine inputs, extern al mono and dac output) ? 8, 11.024, 16, 22.05, 24, 32, 44 .1 and 48 khz sampling rates ? 256x or 384xfs master clock frequency ? i2s serial audio interface mono audio power amplifier ? supply input from main li-ion battery ? 440mw on 8 ohm load ? low power mode for earphone ? programmable volume control (-22 to +20 db) ? fully differential structure, input and output ? 8 ma drain current in full power mode ? power-down mode (consumption less than 2ua) ? minimum external components (dir ect connection of the loudspeaker) applications: mobile phones, digital came ras, pdas, smartpho nes, dect phones, music players 1. description the AT73C213 is a fully integrated, low-cost, combined stereo audio dac and audio power amplifier circuit targeted for li-ion or ni-mh battery powered devices such as mobile phones, smartp hones, pda, dect phones, digita l still cameras, music players or any other type of handheld device where an audio interface is needed. the stereo dac section is a complete high performance, stereo audio digital-to-ana- log converter delivering a 93 db dynamic range. it comprises a multibit sigma-delta modulator with dither, continuous time analog filters and analog output drive circuitry. this architecture provides a high insensitivit y to clock jitter. the di gital interpolation fil- ter increases the sample rate by a factor of 8 using 3 linear phase half-band filters cascaded, followed by a first order sinc interpolator with a factor of 8. this filter elim- inates the images of baseband audio, retaining only the image at 64x the input sample rate, which is eliminated by the analog post filter. optionally, a dither signal can be added that reduces possible noise tones at the output. however, the use of a multibit sigma-delta modulator already provides extremely low noise tone energy. master clock is from 256 or 384 times the input data rate, allowing choice of input data rate up to 50 khz, including standard audio rates of 48, 44.1, 32, 16 and 8 khz. the dac section is followed by a volume a nd mute control and can be simultaneously played back directly through a stereo 32 ohm headset pair of drivers. power management for mobiles (pm) AT73C213 audio interface for portable handsets 2744a?pmgmt?27-jan-05
2 2744a?pmgmt?27-jan-05 AT73C213 the stereo 32 ohm headset pair of drivers also includes a mixer of a linel and liner pair of stereo inputs, as well as a differential monaural auxiliary input (line level). the dac output can be connected through a buffer stage to the input of the audio power ampli- fier, using 2x coupling capacitors the mono buffer stage also includes a mixer of the linel and liner inputs, as well as a diff erential monaural auxilia ry input (line level) which can be, for example, the output of a voice codec output driver in mobile phones. the audio power amplifier is a dual-mode ab cl ass amplifier with differential output and pro- grammable volume control. in full power mode, it is capable of driving an 8-ohm loudspeaker at maximum power of 1w at 5v supply and 440 mw at 3.6v supply. in low power mode, it can drive the same loudspeaker as an earpiece, making it suitable as a handsfree speaker driver in wireless handset application. the volume, mute, power down, de-emphasis controls and 16-bit, 18-bit and 20-bit audio formats are digitally prog rammable via a 4-wire spi bus and the digital audio data are provided through a multi-format i2s interface. 2. block diagram figure 2-1. AT73C213 functional block diagram AT73C213 rstb smode vdig avdd sdin lrfs bclk seri al au dio i/f digital filter liner linel hsr hsl avddhs lolc: -6 to +6db in 3db step 32 driver 32 driver volume control lmpg: -34.5db to +12db in 1.5db step and mute vcm pga digital filter volume control llig: -33 to +12db in 3db step + 20db and mute spi_dout spi_clk spi_csb spi spi_din dac + + llog: -46.5db to 0db in 1.5db step and mute + + gndd mclk ingnd voltage reference vref gndb status registers + pga auxn auxp mono monop monon lphn hpn hpp vbat painn painp cbp dac mono rlig: -33 to +12db in 3db step + 20db and mute rmpg: -34.5db to +12db in 1.5db step and mute volume control volume control rlog: -46.5db to 0db in 1.5db step and mute audio pa rolc: -6 to +6db in 3db step auxg: -33 to +12db in 3db step +20 db and mute apagain -22 to +20db in 3db step
3 2744a?pmgmt?27-jan- AT73C213 2744a?pmgmt?27-jan-05 3. pin description table 3-1. pin description pin name i/o pin type function lphn o 10 analog low power audio stage output hpn o 11 analog negative speaker output vbat i 12 supply audio amplifier supply hpp o 13 analog positive speaker output cbp o 14 analog audio amplifier common mode voltage decoupling painn i 15 analog audio amplifier negative input painp i 16 analog audio amplifier positive input sdin i 17 digital audio interface serial data input bclk i 18 digital audio interface bit clock lrfs i 19 digital audio interface left/right channel synchronization frame pulse mclk i 20 digital audio interface master clock input rstb i 21 digital master reset (active low) smode i 22 digital serial interface selection (to connect to ground) gndd gnd 23 ground digital ground vdig i 24 supply digital supply spi_dout o 25 digital spi data output spi_din i/o 26 digital spi data input spi_clk i 27 digital spi clock spi_csb i 28 digital spi chip select monon o 29 analog negative monaural driver output monop o 30 analog positive monaural driver output auxp i 31 analog audio mono auxiliary positive input auxn i 32 analog audio mono auxiliary negative input vref i 1 analog voltage reference pin for decoupling avdd i 2 supply analog supply (dac + line in + aux + mono out) hsl o 3 analog left channel headset driver output hsr o 4 analog right channel headset driver output avddhs i 5 supply headset driver analog supply linel i 6 analog left channel line in liner i 7 analog right channel line in ingnd i 8 analog line signal ground pin for decoupling vcm i 9 analog common mode reference for decoupling gndb gnd 33 (bottom) ground analog ground
4 2744a?pmgmt?27-jan-05 AT73C213 4. electrical characteristics 5. digital ios all the digital ios: sdin, bclk, lrfs, mclk, rstb, smode, spi_dout, spi_din, spi_clk, spi_csb are referred to as vdig. 6. audio power amplifier 6.1 electrical specifications vbat = 3.6v, t a = 25c unless otherwise noted. high power mode, 100 nf capacitor connected between cbp and gnd audio, 470 nf input capacitors, load = 8 ohms. table 4-1. absolute maximum ratings* operating temperature (industrial)...............-40 c to +85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or ot her conditions beyond those indicated in the operational se ctions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reli- ability. storage temperature ... ............... .............. ... -55c to +150c power supply input on vbat.......................................................... -0.3v to +5.5v on vdig, avdd .............................................. -0.3v to +3.6v table 5-1. digital ios symbol parameter conditions vdig min max unit vil low level input voltage guaranteed input low voltage from 2.4vto 3.3 v -0.3 0.2 x vdig v vih high level input voltage guaranteed input high voltage from 2.4vto 3.3 v 0.8 x vdig vdig + 0.3 v vol low level output voltage iol = 2 ma from 2.4vto 3.3 v 0.4 v voh high level output voltage ioh = 2 ma from 2.4vto 3.3 v vdig - 0.5v v table 6-1. audio power amplifier el ectrical specifications parameter symbol conditions min typ max unit v dd supply voltage unloaded, 100 nf decoupling capacitor to gnd 33.65.5v i dd quiescent current inputs shorted, no load 6 8 ma i ddstby standby current 2a v cbp dc reference vdd/2 v vos output differential offset full gain -20 0 20 mv z in input impedance active state 12k 20k 30k ohm z lfp output load full power mode 6 8 32 ohm z llp output load low-power mode, including r1 100 150 300 ohm c l capacitive load 100 pf psrr power supply rejection ratio 200 to 2 khz differential output 60 db
5 2744a?pmgmt?27-jan- AT73C213 2744a?pmgmt?27-jan-05 bw min low frequency cutoff 1 khz reference frequency 3 db attenuation 470 nf input coupling capacitors 50 hz bw max high frequency cutoff 1 khz reference frequency 3 db attenuation 470 nf input coupling capacitors 20 khz t up output setup time off to on mode voltage already settled input capacitors precharged 10 ms v n output noise max gain, a weighted 120 500 v rms thd hp output distortion high power mode, v dd = 3.6v, 1 khz, pout = 100 mw, gain = 0db 0.3 % thd lp output distortion low power mode, v dd = 3.6v, 1khz, vout = 100m vpp, max gain, load 8 ohms in series with 200 ohms 1% p max maximum power low power mode, v dd = 3.6v, 1 khz, vout = 100 mvpp, max gain, load 8 ohms in series with 200 ohms 440 mw g acc overall gain accuracy -2 0 2 db g step gain step accuracy -0.7 0 0.7 db table 6-1. audio power amplifier el ectrical specifications parameter symbol conditions min typ max unit
6 2744a?pmgmt?27-jan-05 AT73C213 7. audio dac 7.1 electrical specifications avdd, avddhs = 2.8 v, t a = 25c, typical case, unless otherwise noted. all noise and distortion specifications are measured in the 20 hz to 0.425xfs and a-weighted filtered. full-scale levels scale proportiona lly with the analog supply voltage. table 7-1. electrical specifications min typ max units overall operating temperature (ambient) -40 +25 +85 c analog supply voltage (avdd, avddhs) 2.7 2.8 3.3 v digital supply voltage (vdig) 2.4 2.8 3.3 v digital inputs/outputs resolution 20 bits logic family cmos logic coding 2's complement analog performance - dac to line-out/headphone output output level for full scale input (for avdd, avddhs = 2.8 v) 1.65 vpp output common mode voltage 0.5 x avddhs v output load resistance (on hsl, hsr) headphone load line load 16 7 32 10 ohm kohm output load capacit ance (on hsl, hsr) headphone load line load 30 30 1000 150 pf pf signal to noise ratio (-1dbfs @ 1khz input and 0db gain) line and headphone loads 87 92 db total harmonic distortion (-1dbfs @ 1khz input and 0db gain) line load headphone load headphone load (16 ohm) 0.01 0.06 0.5 0.016 0.1 1 % % % dynamic range (measured with -60 dbfs @ 1khz input, extrapolated to full-scale) line load headphone load 88 70 93 74 db db interchannel mismatch 0.1 1 db left-channel to right-channel crosstalk (@ 1khz) -90 -80 db output headset driver level control range -6 6 db output headset driver level control step 3 db
7 2744a?pmgmt?27-jan- AT73C213 2744a?pmgmt?27-jan-05 psrr 1 khz 20 khz 55 50 db db maximum output slope at power up (100 to 220 f coupling capacitor) 3v/s analog performance - line-i n/microphone in put to line-out /headphone output input level for full scale output - 0dbfs level @ avdd, avddhs = 2.8 v and 0 db gain @ avdd, avddhs = 2.8 v and 20 db gain 1.65 583 0.165 58.3 vppm vrms vppm vrms input common mode voltage 0.5 x avdd v input impedance 7 10 kohm signal to noise ratio -1 dbfs @ 1khz input and 0 db gain -21 dbfs @ 1khz input and 20 db gain 81 85 71 db dynamic range (extrapolated to full scale level) -60 dbfs @ 1khz input and 0 db gain -60 dbfs @ 1khz input and 20 db gain 82 86 72 db total harmonic distortion -1dbfs @ 1khz input and 0 db gain -1dbfs @ 1khz input and 20 db gain 0.01 0.018 0.016 0.04 % % interchannel mismatch 0.1 1 db left-channel to right-channel crosstalk (@ 1khz) -90 -80 db analog performance - differen tial mono in put amplifier differential input level for full scale output - 0dbfs level @ avdd, avddhs = 2.8 v and 0 db gain 1.65 583 vppdif mvrms input common mode voltage 0.5xavdd v input impedance 7 10 kohm signal to noise ratio (-1 dbfs @ 1khz input and 0 db gain) 76 80 db total harmonic distortion (-1dbfs @ 1khz input and 0 db gain) -85 -81 db analog performance - pa driver differential output level for full scale input (for avdd, avddhs = 2.8 v) 3.3 vppdif output common mode voltage 0.5 x avddhs v output load 10 kohm 30 pf signal to noise ratio (-1dbfs @ 1khz input and 0db gain) 76 80 db table 7-1. electrical specifications (continued) min typ max units
8 2744a?pmgmt?27-jan-05 AT73C213 total harmonic distortion (-1dbfs @ 1khz input and 0db gain) -75 -71 db master clock master clock maximum long term jitter 1.5 ns pp digital filter performance frequency response (10 hz to 20 khz) 0.1 db deviation from linear phase (10 hz to 20 khz) 0.1 deg passband 0.1 db corner 0.4535 fs stopband 0.5465 fs stopband attenuation 65 db de-emphasis filter performance (for 44.1khz fs) max deviation from ideal response -1 1 db power performance current consumption from analog supply in power on 9.5 ma current consumption from analog supply in power down 10 ma power on settling time from full power down to full power up (vref and vcm decoupling capacitors charge) line in amplifier (line in coupling capacitors charge) driver amplifier (out driver dc blocking capacitors charge) 500 50 500 ms ms ms table 7-1. electrical specifications (continued) min typ max units
9 2744a?pmgmt?27-jan- AT73C213 2744a?pmgmt?27-jan-05 7.2 digital filters transfer function figure 7-1. channel filter figure 7-2. channel filter figure 7-3. de-emphasis filter 10 3 10 4 -12 -10 -8 -6 -4 -2 0 fr of dac decimator with deemphasis fs=44100; osr=128 frequency (hz) gain (db)
10 2744a?pmgmt?27-jan-05 AT73C213 7.3 data interface normal operation is entered by applying correct lrfs, bclk and sdin waveforms to the serial interface, as illustrated in figure 7-4 , figure 7-5 and figure 7-6 . to avoid noise at the output, the reset state is maintained until proper synchronization is achieved in the serial interface. the data interface allows three different data transfer modes. see figure 7-4 , figure 7-5 and figure 7-6 . figure 7-4. 20-bit i2s justified mode figure 7-5. 20-bit msb justified mode figure 7-6. 20-bit lsb justified mode the selection between modes is done using the dintsel<1:0> signal. the data interface always works in slave mode. this means that the lrfs and the bclk sig- nals are provided by the host controller. in order to achieve proper operation, the lrfs and the bclk signals must be synchronous with the mclk master clock signal and their frequency rela- tionship must reflect the selected data mode. for example, if the data mode selected is the 20- bit msb justified, then the bclk frequency must be 40 times higher than the lrfs frequency. r1 r0 l(n-1) l(n-2) l(n-3) ... l2 l1 l0 r(n-1) r(n-2) r(n-3) ... r2 r1 r0 bclk lrfs sdin r0 l(n-1) l(n-2) l(n-3) ... l2 l1 l0 r(n-1) r(n-2) r(n-3) ... r2 r1 r0 l(n-1) bclk lrfs sdin r0 l(n-1) l(n-2) ... l1 l0 r(n-1) r(n-2) ... r1 r0 l(n-1) bclk lrfs sdin dintsel <1:0> format 00 i2s justified 01 msb justified 1x lsb justified
11 2744a?pmgmt?27-jan- AT73C213 2744a?pmgmt?27-jan-05 7.4 timing specifications figure 7-7. data interface timing diagram table 7-2. data interface timing parameters parameter min typ max unit td1 delay from mclk rising edge to bclk edges 2.5 7.5 ns td2 delay from bclk falling edge to lrfs edges 0 5 ns ts3 din set-up time before bclk rising edge 10 ns th3 din hold time after bclk rising edge 10 ns mclk bclk 1 1 n 19n+1 20n 20 m/2+1 m m/2.n+1 m/2.(n+1) (m-1).n+1 m.n lrfs sdin td1 td2 ts3 th3
12 2744a?pmgmt?27-jan-05 AT73C213 8. spi interface 8.1 architecture the spi is a three-wire bi-directional asynchronous serial link. it works only in slave mode. the protocol is the following: figure 8-1. spi architecture 8.2 spi protocol on spi_din, the first bit is a read/write bit. 0 indicates a write operation, while 1 is for a read operation. the seven following bits are used for the register address and the eight last ones are the write data. for both address and data, the most significant bit is the first one. in case of a read operation, spi_dout provides the contents of the read register, msb first. the transfer is enabled by the csb signal acti ve low. when no operation is being carried out, spi_dout is set high impedance to allow sharing of mcu serial interface with other devices. the interface is reset at every rising edge of spi_csb in order to come back to an idle state, even if the transfer does not succeed. the spi is synchronized with the serial clock spi_clk. falling edge latches spi_din input and rising edge shifts spi_dout output bits. note that mclk must run during any spi write access from address 0x00 to 0x0d. rw a6 a5 a4 a3 a2 a1 d7 d6 d5 d3 d7 d6 d5 d4 d1 d0 d2 d3 d0 d1 d2 d4 a0 spi_dout spi_din spi_clk spi_csb
13 2744a?pmgmt?27-jan- AT73C213 2744a?pmgmt?27-jan-05 8.3 spi interface timing figure 8-2. spi timing thsdi tssen tc twl twh thsen tssdi spi_dout spi_din spi_clk tdsdo thsdo spi_csb table 8-1. spi timing parameters parameter description min max tc spi_clk min period 100 ns - twl spi_clk min pulse width low 50 ns - twh spi_clk min pulse width high 50 ns - tssen setup time spi_csb falling to spi_clk rising 50 ns - thsen hold time spi_clk falling to spi_csb rising 50 ns - tssdi setup time spi_din valid to spi_clk falling 20 ns - thsdi hold time spi_clk falling to spi_din not valid 20 ns - tdsdo delay time spi_clk risi ng to spi_dout valid - 20 ns thsdo hold time spi_clk rising to spi_dout not valid 0 ns -
14 2744a?pmgmt?27-jan-05 AT73C213 8.4 spi user interface note: msb = bit 7, lsb = bit 0 table 8-2. spi register mapping address register name access reset state 0x00 dac_ctrl dac control read/write 0x00 0x01 dac_llig dac left line in gain read/write 0x05 0x02 dac_rlig dac right line in gain read/write 0x05 0x03 dac_lpmg dac left master playback gain read/write 0x08 0x04 dac_rpmg dac right master playback gain read/write 0x08 0x05 dac_llog dac left line out gain read/write 0x00 0x06 dac_rlog dac right line out gain read/write 0x00 0x07 dac_olc dac output level control read/write 0x22 0x08 dac_mc dac mixer control read/write 0x09 0x09 dac_csfc dac clock and sampling frequency control read/write 0x00 0x0a dac_misc dac miscellaneous read/write 0x00 0x0c dac_prech dac precharge control read/write 0x00 0x0d dac_auxg dac auxiliary input gain control read/write 0x05 0x10 dac_rst dac reset read/write 0x00 0x11 pa_crtl power amplifier control read/write 0x00
15 2744a?pmgmt?27-jan- AT73C213 2744a?pmgmt?27-jan-05 8.5 dac control register register name: dac_ctrl reset state: 0x00 access: read/write onlnil left channel line in amplifier (l to power down, h to power up) onlnir right channel line in amplifier (l to power down, h to power up) onlnol left channel line out driver (l to power down, h to power up) onlnor right channel line out driver (l to power down, h to power up) ondacl left channel dac (l to power down, h to power up) ondacr right channel dac (l to pow er down, h to power up) onauxin differential mono auxiliary input amplifier (l to po wer down, h to power up) onpadrv differential mono pa driver (l to power down, h to power up) 76543210 onpadrv onauxin ondacr ondacl onlnor onlnol onlnir onlnil
16 2744a?pmgmt?27-jan-05 AT73C213 8.6 dac left line in gain register register name: dac_llig reset state: 0x05 access: read/write llig: left channel line in analog gain selector 76543210 000 llig llig<4:0> gain unit 00000 20 db 00001 12 db 00010 9 db 00011 6 db 00100 3 db 00101 0 db 00110 -3 db 00111 -6 db 01000 -9 db 01001 -12 db 01010 -15 db 01011 -18 db 01100 -21 db 01101 -24 db 01110 -27 db 01111 -30 db 10000 -33 db 10001 < -60 db
17 2744a?pmgmt?27-jan- AT73C213 2744a?pmgmt?27-jan-05 8.7 dac right line in gain register register name: dac_rlig reset state: 0x05 access: read/write rlig: right channel line in analog gain selector 76543210 000 rlig rlig<4:0> gain unit 00000 20 db 00001 12 db 00010 9 db 00011 6 db 00100 3 db 00101 0 db 00110 -3 db 00111 -6 db 01000 -9 db 01001 -12 db 01010 -15 db 01011 -18 db 01100 -21 db 01101 -24 db 01110 -27 db 01111 -30 db 10000 -33 db 10001 < -60 db
18 2744a?pmgmt?27-jan-05 AT73C213 8.8 dac left master playback gain register register name: dac_lmpg reset state: 0x08 access: read/write lmpg: left channel master playback digital gain selector 76543210 00 lmpg lmpg<5:0> gain unit lmpg<5:0> gain unit 000000 12.0 db 010001 -13.5 db 000001 10.5 db 010010 -15.0 db 000010 9.0 db 010011 -16.5 db 000011 7.5 db 010100 -18.0 db 000100 6.0 db 010101 -19.5 db 000101 4.5 db 010110 -21.0 db 000110 3.0 db 010111 -22.5 db 000111 1.5 db 011000 -24.0 db 001000 0.0 db 011001 -25.5 db 001001 -1.5 db 011010 -27.0 db 001010 -3.0 db 011011 -28.5 db 001011 -4.5 db 011100 -30.0 db 001100 -6.0 db 011101 -31.5 db 001101 -7.5 db 011110 -33.0 db 001110 -9.0 db 011111 -34.5 db 001111 -10.5 db 100000 mute db 010000 -12.0 db
19 2744a?pmgmt?27-jan- AT73C213 2744a?pmgmt?27-jan-05 8.9 dac right master playback gain register register name: dac_rmpg reset state: 0x08 access: read/write rmpg: right channel master playback digital gain selector 76543210 00 rmpg rmpg<5:0> gain unit rmpg<5:0> gain unit 000000 12.0 db 010001 -13.5 db 000001 10.5 db 010010 -15.0 db 000010 9.0 db 010011 -16.5 db 000011 7.5 db 010100 -18.0 db 000100 6.0 db 010101 -19.5 db 000101 4.5 db 010110 -21.0 db 000110 3.0 db 010111 -22.5 db 000111 1.5 db 011000 -24.0 db 001000 0.0 db 011001 -25.5 db 001001 -1.5 db 011010 -27.0 db 001010 -3.0 db 011011 -28.5 db 001011 -4.5 db 011100 -30.0 db 001100 -6.0 db 011101 -31.5 db 001101 -7.5 db 011110 -33.0 db 001110 -9.0 db 011111 -34.5 db 001111 -10.5 db 100000 mute db 010000 -12.0 db
20 2744a?pmgmt?27-jan-05 AT73C213 8.10 dac left line out gain register register name: dac_llog reset state: 0x00 access: read/write llog: left channel line out digital gain selector 76543210 00 llog llog<5:0> gain unit llog<5:0> gain unit 000000 0.0 db 010000 -24.0 db 000001 -1.5 db 010001 -25.5 db 000010 -3.0 db 010010 -27.0 db 000011 -4.5 db 010011 -28.5 db 000100 -6.0 db 010100 -30.0 db 000101 -7.5 db 010101 -31.5 db 000110 -9.0 db 010110 -33.0 db 000111 -10.5 db 010111 -34.5 db 001000 -12.0 db 011000 -36.0 db 001001 -13.5 db 011001 -37.5 db 001010 -15.0 db 011010 -39.0 db 001011 -16.5 db 011011 -40.5 db 001100 -18.0 db 011100 -42.0 db 001101 -19.5 db 011101 -43.5 db 001110 -21.0 db 011110 -45.0 db 001111 -22.5 db 011111 -46.5 db 100000 mute db
21 2744a?pmgmt?27-jan- AT73C213 2744a?pmgmt?27-jan-05 8.11 dac right line out gain register register name: dac_rlog reset state: 0x00 access: read/write rlog: right channel line out digital gain selector 76543210 00 rlog rlog<5:0> gain unit rlog<5:0> gain unit 000000 0.0 db 010000 -24.0 db 000001 -1.5 db 010001 -25.5 db 000010 -3.0 db 010010 -27.0 db 000011 -4.5 db 010011 -28.5 db 000100 -6.0 db 010100 -30.0 db 000101 -7.5 db 010101 -31.5 db 000110 -9.0 db 010110 -33.0 db 000111 -10.5 db 010111 -34.5 db 001000 -12.0 db 011000 -36.0 db 001001 -13.5 db 011001 -37.5 db 001010 -15.0 db 011010 -39.0 db 001011 -16.5 db 011011 -40.5 db 001100 -18.0 db 011100 -42.0 db 001101 -19.5 db 011101 -43.5 db 001110 -21.0 db 011110 -45.0 db 001111 -22.5 db 011111 -46.5 db 100000 mute db
22 2744a?pmgmt?27-jan-05 AT73C213 8.12 dac output leve l control register register name: dac_olc reset state: 0x22 access: read/write lolc: left channel output level control selector lshort: left channel short circuit indicator persistent; after being set, bit is not cleared automatically even after the short circuit is eliminated; must be cleared by re set cycle or direct register write operation. rolc: right channel output level control selector rshort: right channel short circuit indicator persistent; after being set, bit is not cleared automatically even after the short circuit is eliminated; must be cleared by re set cycle or direct register write operation. 76543210 rshort rolc lshort lolc lolc gain unit 000 6 db 001 3 db 010 0 db 011 -3 db 100 -6 db rolc gain unit 000 6 db 001 3 db 010 0 db 011 -3 db 100 -6 db
23 2744a?pmgmt?27-jan- AT73C213 2744a?pmgmt?27-jan-05 8.13 dac mixer control register register name: dac_mc reset state: 0x09 access: read/write lmsmin1: left channel mono/stereo mixer left mixed input enable (h to enable, l to disable) lmsmin2: left channel mono/stereo mixer right mixed input enable (h to enable, l to disable) rmsmin1: right channel mono/stereo mixer left mi xed input enable (h to enable, l to disable) rmsmin2: right channel mono/stereo mixer right mi xed input enable (h to enable, l to disable) invl: left channel mixer output invert (h to enable, l to disable) invr: right channel mixer output invert (h to enable, l to disable) 8.13.1 digital mixer control the audio dac features a digital mixer that allows the mixing and selection of multiple input sources. the mixing/multiplexing functions are described in figure 8-3 and table 8-3 . figure 8-3. digital mixer functions note: when the two mixer inputs are selected, a -6 db gain is applied to the output signal. when only one input is selected, no gain is applied. 76543210 0 0 invr invl rmsmin2 rmsmin1 lmsmin2 lmsmin1 volume control volume control volume control volume control left channel right channel from digital filters to dacs + + 1 2 2 1 table 8-3. digital mixer signal description signal description lmsmin1 left channel mono/stereo mixer left mixed input enable - high to enable, low to disable lmsmin2 left channel mono/stereo mixer right mixed input enable - high to enable, low to disable rmsmin1 right channel mono/stereo mixer left mixed input enable - high to enable, low to disable rmsmin2 right channel mono/stereo mixer right mixed input enable - high to enable, low to disable
24 2744a?pmgmt?27-jan-05 AT73C213 8.14 dac clock and sampli ng frequency control register register name: dac_csfc reset state: 0x00 access: read/write ovrsel: master clock selector l to 256 x fs, h to 384 x fs master clock and sampling frequency selection table 8-4 describes the modes available for master clock and sampling frequency selection. 76543210 000ovrsel0000 table 8-4. master clock modes ovrsel master clock 0256 x fs 1384 x fs
25 2744a?pmgmt?27-jan- AT73C213 2744a?pmgmt?27-jan-05 8.15 dac miscellaneous register register name: dac_misc reset state: 0x00 access: read/write nbits<1:0>: data in terface word length the selection of input sample size is done using the nbits field. deempen: de-emphasis enable (l to disable, h to enable) to enable the de-emphasis filtering the deemphen signal must be set to high. dithen: dither enable (l to disable, h to enable) the dither option (added in the playback channel) is enabled by setting the dithen signal to high. dintsel<1:0>: i2s da ta format selector the selection between modes is done using the dintsel<1:0> signal. vcmcapsel: vcm decoupli ng capacitor selector l for 10 f, h for 100 f 76543210 vcmcapsel 0 dintsel dithen deempen nbits nbits <1:0> format 00 16 bits 01 18 bits 10 20 bits dintsel<1:0> format 00 i2s justified 01 msb justified 1x lsb justified
26 2744a?pmgmt?27-jan-05 AT73C213 8.16 dac precharge control register register name: dac_prech reset state: 0x00 access: read/write onmstr: master power on control (l to power down, h to power up) prcharge: master pre-charge (h to charge) prchargelnil: left channel line in pre-charge (h to charge) prchargelnir: right channel line in pre-charge (h to charge) prchargelnol: left ch annel line out pre-charge (h to charge) prchargelnor: right channel line out pre-charge (h to charge) prchargeauxin: differential mono auxilia ry input pre-charge (h to charge) prchargepadrv: differential mono pa driver pre-charge (h to charge) 76543210 prchgpdrv prchgaux1 prchglnor prchglnol prchglnir prchglnil prchg onmstr
27 2744a?pmgmt?27-jan- AT73C213 2744a?pmgmt?27-jan-05 8.17 dac auxiliary input gain control register register name: dac_auxg reset state: 0x05 access: read/write auxg: differential mono auxili ary input analog gain selector 76543210 000 auxg auxg<4:0> gain unit 00000 20 db 00001 12 db 00010 9 db 00011 6 db 00100 3 db 00101 0 db 00110 -3 db 00111 -6 db 01000 -9 db 01001 -12 db 01010 -15 db 01011 -18 db 01100 -21 db 01101 -24 db 01110 -27 db 01111 -30 db 10000 -33 db 10001 < -60 db
28 2744a?pmgmt?27-jan-05 AT73C213 8.18 dac reset register register name: dac_rst reset state: 0x00 access: read/write rstz: active low reset of the audio codec resfilz: active low reset of the audio codec filter resmask: active high reset mask of the audio codec see ?supplies and start-up? on page 30 . 76543210 ?????resmaskresfilzrstz
29 2744a?pmgmt?27-jan- AT73C213 2744a?pmgmt?27-jan-05 8.19 pa control register register name: pa_ctrl reset state: 0x00 access: read/write apagain<3:0>: audio power amplifier gain apalp: audio power amplifier low power bit 0: high power 1: low power apaprech: audio power amplifier precharge bit apaon: audio power amplifier on bit 76543210 ? apaon apaprech apalp apagain apagain<3:0> gain (db) apagain<3:0> gain (db) 0000 -22 1000 -1 0001 20 1001 -4 0010 17 1010 -7 0011 14 1011 -10 0100 11 1100 -13 0101 8 1101 -16 0110 5 1110 -19 0111 2 1111 -22 apaon apaprech operating mode 0 0 stand-by 0 1 input capacitors precharge 10active mode 1 1 forbidden state
30 2744a?pmgmt?27-jan-05 AT73C213 9. supplies and start-up in operating mode, vbat (supply of the audio power amplifier) must be between 3v and 5.5v and avdd, avddhs and vdig must be inferior or equal to vbat. a typical application is vbat connected to a battery and avdd, avddhs and vdig supplied by regulators. vbat must be pres ent at the same time or before avdd, avddhs and vdig. rstb must be active (0) until the voltages are stable and reach the proper values. to avoid noise issues, it is recommended to us e ceramic decoupling capacitors for each supply close to the package. see figure 11-1 on page 32 . the track of the supplies must be optimized to minimize the resistance, especially on vbat where all the current from the power amplifier comes from. hpn and hpp must be routed symmetrically and the resistance must be minimized. 9.1 audio dac start-up sequences in order to minimize the noise during the st art-up, a specific sequence should be applied. 9.1.1 power on example path dac to headset output 1. write @0x10 => 0x03 (deassert the reset) 2. write @0x0c => 0xff (precharge + master on) 3. write @0x00 => 0x30 (onlnol and onlonor set to 1) 4. delay 500 ms 5. write @0x0c => 0x01 (precharge off + master on) 6. delay 1ms 7. write @0x00 => 0x3c (onlnol, onlnor, ondacr and ondacl set to 1) 9.1.2 power off example 1. write @0x00 => 0x30 (ondacr and ondacl set to 0) 2. write @0x0c => 0x00 (master off) 3. delay 1ms 4. write @0x00 => 0x00 (all off) 9.1.3 i2s example in order to prevent i2s from generating noise at the output (for example a mp3 player switching from one song to another): 1. set ondac to 0 ((bit 4 and 5 in register @0x00) 2. stop i2s and mclk when i2s is restarted, in order to prevent noise generation at the output: 1. start mclk 2. write @0x10 => 0x07 (rstmsk=1) 3. write @0x10 => 0x04 (resfilz=0, rstz=0) 4. write @0x10 => 0x07 (resfilz=1, rstz=1)
31 2744a?pmgmt?27-jan- AT73C213 2744a?pmgmt?27-jan-05 5. write @0x10 => 0x03 (rstmsk=0) 6. delay 5 ms 7. set ondac to 1 (bit 4 and 5 in register @0x00) 8. reprogram all dac settings (audio format, gains, etc.) 9. start i2s. 9.2 audio power amplifier power on sequence to avoid an audible ?click? at start-up, the input capacitors must be pre-charged before the power amplifier. 1. at start-up, set apaon off, apagain<3:0> set to -22 db, set apaprecharge to 1. 2. wait 50 ms minimum. 3. then disable apaprech and set apaon. 4. wait 10 ms min time. 5. set the gain to the value chosen. 9.2.1 audio power amplifier power off sequence to avoid an audible ?click? at power-off, the gai n should be set to the minimum gain (-22 db) before turning off the power amplifier. 10. current consumption in different modes table 10-1. current consumption in different modes mode current consumption (typ) current consumption (max) unit 0: off 5 12 ua 1: standby 250 350 ua 2: dac playback through stereo headset (current in the load not included) 5100 6700 ua 3: stereo dac playback to audio pa (current in the load not included) 9500 13500 ua 4: playback from mono in to audio pa (current in the load not included) 6200 10500 ua 5: playback from stereo line input to stereo headset (current in the load not included) 1600 3300 ua
32 2744a?pmgmt?27-jan-05 AT73C213 11. application diagram figure 11-1. application using one li-ion battery AT73C213 vref auxp painn bclk gndd lphn linel liner hsl hsr gndb lrfs sdin smode rstb mclk spi_din spi_csb spi_clk spi_dout ingnd cbp hpn painp hpp vbat monon monop auxn vdig avdd vcm 470n c4 mono input (-) 2.8v from ldo 2.8v from ldo 3.6 v (li-ion or 3 x nimh or nicd) battery mono differential input 100n c7 8 ohm loudspeaker 10u c11 32 ohm headset or line out 470n c8 100u c5 100u c6 470n c3 32 32 stereo line input (e.g. fm radio) 8 470n c1 10u c9 22u c16 470n c15 470n c12 200 r1 10u c10 r l mono input (+) avddhs i2s spi reset active low c17 c18 c19 100n 100n 100n audio pa ref dig audio dac
33 2744a?pmgmt?27-jan- AT73C213 2744a?pmgmt?27-jan-05 12. package drawing figure 12-1. package outline notes: 1. all dimensions are in mm. 2. drawing is for general information only. refer to jedec drawing mo-220 for additional information. figure 12-2. package drawing with pin 1 and marking 33 1 AT73C213 y y ww xxxxxxxxx 2 ? 32 31 ? 33 1 AT73C213 y y ww xxxxxxxxx 2 ? 32 31 ?
34 2744a?pmgmt?27-jan-05 AT73C213 13. revision history table 13-1. revision history doc. rev. date comments change request ref. 2744a 27-jan-05 first issue.
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